News, views and contacts from the global Semiconductor industry

Small Wonder

1 March 2008 Michael J Fister

Chips are now so complex that electronic design automation is vital for future performance. Jim Banks speaks to Michael J Fister, the president and CEO of Cadence Design Systems, about the complexities of working at the nanometre scale to increase performance and functionality.

In a world where demand for improved performance from microchips is never satisfied, chip designers must work at minute scales in order to provide the density and speed that today's electronic products demand. This is clearly challenging and current levels of performance would have been unobtainable without advances in electronic design automation (EDA).


EDA – sometimes referred to as electronic computer-aided design (ECAD) – focuses on the design and production of printed circuit boards, integrated circuits and other electronic systems. Automation enables designers to work at the nanometre scale to help chips pack more punch.

From here on, the sophistication of EDA will determine the future capability of microchips.

"I've been in the semiconductor business all my life and I expect a relentless push for greater processor performance because of the demand for products, but the challenges of the physics and the densities that we work at are great. After all, development is not only about having a billion transistors on a chip but also about having them all work," says Michael J Fister, the president and chief executive officer of Cadence Design Systems.

Fister has impressive insight about chip development. Not surprising, given that his background includes 17 years at Intel Corporation, where he was most recently the senior vice president and general manager of Enterprise Platforms Group, which designs, markets and supports the building blocks for enterprise computing. He oversaw Intel's growing share of this market and the introduction of the Itanium processor family.

In his previous posts as the vice president and general manager of Performance Microprocessor Group, he managed Intel's IA-32 processor development organisation and was responsible for the design, development and marketing of IA-32 processors – including the last versions of the Intel486 and the entire line of Pentium Pro, Pentium II, Pentium III, Celeron, Pentium II Xeon, and Pentium III Xeon processors.

Fister believes that the complexity encountered at smaller scales is the biggest challenge going forward and that Cadence can play an important role in bringing the various elements of the semiconductor industry together.

"We help humans to manage that complexity. We are a glue element. The industry is working at fever pitch, as without acceleration in automation it will grind to a halt because of the complexity," he says.


The industry itself has become more of a disaggregated eco-system, with companies focusing on specific elements of the process. Fister feels it is part of Cadence's remit to ensure that these separate development efforts inform each other and that only through closer collaboration can many of the greatest challenges be overcome.

"The industry has become a divided eco-system, with companies focusing on specific elements."

"EDA is among the first elements to disaggregate, though this has also burgeoned in wafer fabrication. The pressure is on us to reaggregate. We drive the design and development methods for chips," says Fister.

Cadence Design Systems is the world's leading provider of EDA technologies and engineering services. It provides leading-edge electronic design solutions to accelerate the move to volume production of advanced IC and system designs. Its technologies, methodologies and services help clients design and verify advanced semiconductors, printed circuit boards and other systems for consumer electronics, networking and telecommunications equipment and computer systems.

"We handle those processes so that our customers can raise their efforts to the next level of abstraction," says Fister.

The fast pace that characterises the semiconductor market has always put pressure on chip manufacturers. In some ways the challenges of complexity are nothing new, though the order has changed considerably.

"When I first came into the industry the focus was on military, defence and similar environments for high-performance computing. They expected continuous improvement, but they did not understand the complexity – they just wanted it to work," says Fister.


Some issues, however, have become far more critical over time. At the moment, power is a key focus for many developers. 'Power is the single functional element that people see as a roadblock,' says Fister. Beyond that roadblock lies the capability to design and produce more power-efficient electronic devices. To get to the other side Cadence believes the greatest gains in achieving low-power technology can be made at the architectural level. They've already been investing in technologies that enable IP re-use and portability.

To ensure that efforts to improve power efficiency pursue common goals and are the result of collaborative efforts, Cadence is playing a prominent role in the Power Forward Initiative and the Silicon Integration Initiative.


In May 2006, Cadence announced the formation of the Power Forward Initiative, which brings together many interested parties to formulate strategies to overcome the obstacles to lower power IC design – a pressing issue for the electronics industry.

Development is not only about having a billion transistors on a chip, but also about having them all work."

The initiative draws on the expertise of these and other leading technology companies, linking design, verification and implementation expertise to reduce risk and increase predictability in chip power reduction. The initial goal has been for members to work towards adopting a new automated design infrastructure to reduce chip power consumption.

In 2007, the Power Forward Initiative started a new, open standardisation process to produce a specification for capturing essential design intent for power and to link the design, implementation and verification domains.


Si2 is an organisation that brings together industry-leading semiconductor systems and EDA and manufacturing companies, which are focused on improving the way integrated circuits are designed and manufactured. The primary goals are to speed time-to market, reduce costs and meet the challenges of sub-micron design.

Si2 has positioned itself to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to many of the challenges facing the semiconductor industry. Over 100 companies from all parts of the silicon supply chain are members of Si2.


Cadence's own approach is to look at turning off parts of a chip when they are not being used. Voltage isolation islands and the use of multiple VPs are being examined, though Fister recognises that this must be done without compromising the designer's intention in terms of the chip's operation and performance. The company has developed a technique that saves the state of the chip areas that are turned off.

"Look at the example of new, energy efficient buildings, which conserve power by turning lights off in areas of the building that are not in use. The architecture can also change to improve energy use. That is where chip development is at now. The designs are so complex, however, that you need to ensure you can find the right switch to turn the lights on again," says Fister.

There are a host of other challenges to address, including productivity and time-to-market, so it may seem hard for the industry to concentrate its efforts but Fister believes that all of these challenges must be faced head on. After all, they are not about to disappear.

"You have to embrace these challenges, otherwise you will simply be daunted by them. You have to look at each problem in as big a piece as possible and follow it through end-to-end. You can't just pursue the technological points of light," says Fister.


Fister firmly believes that building the next generation of microchips will require extensive, industry-wide collaboration, otherwise complexity and the pressures constantly applied by end users will prove too much.

"Current levels of performance would have been unobtainable without advances in EDA."

Fister feels that a strong trend towards deeper, more involved partnerships will dominate the years ahead so it is vital for companies at all stages of the semiconductor chain to improve their collaborative processes.

"Some chips, including our high-performance processor, are so complex that no single person can understand all its intricacies. When I started in the industry I could handle all the elements myself," says Fister.

Partnering is not just a new name for the supplier / client relationship. For Fister, it must mean something more than that – a long-term commitment to shared goals and a willingness to embed a close, collaborative culture.

"Some customers have consolidated their relationships with us, which helps to attack the virtual disaggregation in the industry. They have built relationships with partners in ERP systems and supply chain management and now they are partnering in EDA, too," says Fister.

In 2007, for instance, Hitachi sets up a new design infrastructure with Cadence to reduce design-cycle time by 40%. Cadence also has a long-standing partnership with Freescale, adding the latter's semiconductor development expertise to Cadence's strength in IC design software, hardware and services. Cadence is Freescale's primary vendor for electronic design automation (EDA) tools and services.

Often, a committed client partnership demands that design teams be more globally dispersed, so that they can be close to the customers. Cadence, for instance, has to operate in many centres around the world in order to service worldwide customers such as NEC.

"There is value in the good old-fashioned process of pursuing collocality with customers. You need that global presence now and it will only become more important in the future," says Fister.


The need for closer relationships in the EDA arena is reflected in the consolidation that has happened in the sector. Clients are turning to established companies to partner them in their long-term development efforts.

"Complexity encountered at smaller scales is the biggest challenge going forward."

Part of the ongoing success of EDA companies like Cadence will no doubt depend on their ability to form closer relationships, not only with clients, but also with other sectors within the semiconductor industry. Automation, after all, will only play a greater role in chip design and manufacture in the years to come.

"That is why companies like Cadence will be more important going forward. The focus on automation will leave the expert minds in the industry to focus on the larger, more complex elements of chip design," believes Fister.

The market has a constant thirst for innovation, such as Cadence's technique of embedding software into chips.

"We have added software to our chips to allow functionality in different applications. The processor cores have a software component, which increases the ramp rate of the end device. These platform dynamics are part of our solution-based approach," says Fister.

Many more challenges certainly lie ahead for the industry, but for now tremendous effort is being put into improving chip performance, cutting down the design cycle and reducing the power demands of semiconductors. With the right cross-industry commitment, the industry will soon be able to move to the next level of complexity.