The pressure of Moore's law has led to a potential impasse. Traditional semiconductor materials cannot scale further and the potential replacements present numerous developmental difficulties. The October 2004 SEMATECH symposium in San Diego explored possible ways forward and the likelihood of a long-term connectivity solution.
Much of the semiconductor industry's success during the past 30 years was due to the ability to increase device density while improving performance. In the mid-1980s, a shift from bi-polar technologies to CMOS-based devices overcame the first major barrier on this road. Now, the industry is once again at a critical stage; conventional scaling principles have hit physical material limits.
The switch from Al-based interconnect to copper in high-performance circuits, and the implementation of technologies such as strained silicon and silicon-on-insulator are feasible solutions. The introduction of advanced dielectric systems such as high-k gate stacks and low-k effective (keff) interconnects is also promising, but complex.
At the October 2004 SEMATECH symposium, the keff challenge was discussed from the views of technological development for 45nm and beyond; interconnect systems (critical issues and development needs); and circuit design. Some of the key outcomes and findings of these discussions are presented here.
KEFF VERSUS KBULK
There are several reasons why keff, rather than the bulk k value of the dielectric by itself is the key predictor of interconnect capacitance performance. Keff is a complex function of the material systems, the unit processes involved and the integration schemes employed. It measures the effect of assist layers, potential damage sustained by the dielectric during the patterning process, and the subsequent replacement of those layers with a single virtual material. The k value of the virtual material is adjusted using computer models until it matches the measured capacitance of the complex system. The final k value of the virtual material is defined as the effective k value of the structure. While this captures most aspects of dielectric interconnect performance, it is a convoluted function of numerous effects that can either increase or decrease the keff of the overall system.
OUTLOOK AND PREDICTIONS
The International Technology Roadmap for Semiconductors (ITRS) 2004 predicts the use of materials with bulk k values of 2.7 in current, state-of-the-art 90nm technology devices. Yet most manufacturers are struggling even to implant materials with values between 2.8 and 3.2. Interestingly, the predicted effective k value is not lagging behind as far as might be expected from the difference in kbulk. This can be attributed mostly to efforts to drive down the k value and the thickness of so-called assist layers that include etch-stop, cap and hard-mask materials.
At the 65nm node, it is unlikely that the materials with a predicted kbulk of <2.4 will be used. Instead, manufacturers plan to extend 90nm solutions by using incremental materials and improving integration as the technology matures. The consequence will be kbulk values of ~2.7 and a preference for dense or micro-porous materials. The first true ultra-low-k materials will see their debut at 45nm, though not with a k-bulk of 2.1. Conservative values at 2.3–2.4 are more likely.
Setting aside the manufacturability issues that already plague 90nm technologies, such as degraded mechanical integrity and thermal properties, the achievable keff will depend on the availability of lower-k assist layers, alternate copper capping schemes and process technologies that cause minimal damage to the low-k dielectric. If those materials and technologies can be implemented, modelling suggests that keff values of ~2.5 are attainable.
Key hurdles in the development and integration of low-k materials are their degraded thermo-mechanical properties, which are represented by the correlation of k value and Young's Modulus (see Figure 1).
Independent of material type (pure organic, methylsilsesquioxane or SiCOH) or deposition technique (Chemical Vapour Deposition [CVD] or spin-on), this general trend of lower modulus with lower k value is fundamentally dictated by the physics of density and electrical polarisability. Most materials in the k<2.4 regime contain meso-pores (discrete pores of sizes above ~1nm) in the final film to reduce the overall amount of polarisable bonds. Usually, the higher the modulus and the lower the k value of the dense matrix, the higher the mechanical strength will be after introduction of porosity to reach the target k regime of ~2.3.
Some interesting developments in this area investigate dense or micro-porous materials that combine in low-k structural components of strong atomic bonding and polarisability to simultaneously achieve a high modulus (<20Gpa) and low k value (<2.5). Research into self-assembled, highly structured and controlled pores are other promising developments. Meanwhile, work on alternatives to conventional furnace cure processes for low-k materials are starting to demonstrate considerable improvements in mechanical properties without significantly compromising k values.
While potential k=2.3 materials for both CVD and spin-on deposition techniques are now emerging, the evolution of low permittivity assist layer systems is still in its early stages. As keff modelling predicts, the k value and thickness of these layers have a profound impact on overall capacitance performance. Figure 1 compares the keff of a system using k=4.5 etch-stop and cap layers at thicknesses of 50nm and 25nm with one of k=2.8 at 50nm thickness as a function of the bulk permittivity. It clearly shows that simple thickness scaling of existing CVD SiC-based assist layers is not a viable scaling route. Upon further optimisation for chemical susceptibility and etch selectivity, bulk low-k materials of the 90nm technology generation might become the materials of choice for assist systems at the 45nm node.
CRITICAL PROCESS TECHNOLOGIES
Improvements in unit process technology have to accompany advancements in materials systems to provide manufacturable solutions. The foremost challenges are in the etch, ash and cleans module.
Chemical species can potentially penetrate deep into the porous low-k, and residuals could get trapped and react in subsequent heat treatments. Ion impingement on sidewalls and re-sputtered species from the etch front can contribute to sidewall densification and bleaching of C-H groups from the dielectric matrix. Compositional, chemical and structural changes in sensitive low-k materials will almost always result in increased k value, deteriorated electrical characteristics and reliability issues.
Optimised etch chemistries and process parameters can minimise the risk of carbon-depleted sidewall layers. What's more, some chemical agents – hexamethyldisilizane, for example – have shown encouraging results in restoring low-k properties and preventing the formation of silanol groups and water absorption post-etch. Resist strip has evolved into directional ashing, while the optimised chemistry largely depends on the low-k materials and ash rate. In manufacturing, however, it will be extremely important to manage etch and ash reactor conditions and polymer volume to achieve optimum results for a given product and level mix.
Post-etch wet cleaning mostly has to remove CFH-like polymers without damaging the dielectric or causing under-cutting. Despite having shown some promising lab-scale results, emerging clean technologies that use supercritical CO2 as the carrier agent have yet to prove that they are cleaner and more cost effective than conventional wet cleaning.
Lower k via-etch stop, metal copper cap, trench etch-stop free patterning, pore-sealing, hard-mask removal during copper and barrier polish are all necessary integration features for a successful keff performance. These challenges can all be tackled by conventional means, but at the risk of over-engineering an interconnect system at diminishing keff return. Some innovative solutions under investigation include post-etch or post-CMP porogen removal or the use of sacrificial materials during processing of a single or dual-damascene level, which is replaced after copper lines are formed by the actual low-k. Such options could simplify integration significantly and solve key concerns such as pore sealing and low-k damage.
Another important integration-related consideration is sensitivities to process variations. Within-chip, within-wafer or wafer-to-wafer critical dimensions, etch depth, profile and CMP over-polish, among others, control changes in keff values. Simulation work has shown that such process variations can result in significant differences in keff and product functionality (see figure 2). No damage to the low-k is taken into account. Careful analysis of process tolerances resulting from a given integration scheme are key to optimising overall parametric performance and interconnect reliability.
CIRCUIT DESIGN AND INTERCONNECT CAPACITANCE
In conclusion, keff scaling to values of ~2.5 at the 45 and 32nm nodes will be extremely challenging from the technology, manufacturability and cost performance standpoints. Individual solutions will be driven by circuit design needs. For gate-dominated devices, for example, performance improvements in capacitance play a smaller role compared with interconnect-dominated circuits where metal line length demands low wiring capacitance for power, signal delay and crosstalk performance. Estimates suggest that in inter-connect-dominated circuits, a keff improvement of 20% (from 3.0 to 2.4) results in an overall performance improvement of 10%. In terms of power density, lower keff can only help to alleviate some of the active power concerns and will not contribute to lower passive consumption.
TOWARDS GREATER CONNECTIVITY
Right now, there is no clear pathway beyond a keff of 2.5. Defining one would require the development of highly porous bulk dielectrics or the elimination of almost all assist layers. Also to be considered is the fact that it might not be possible to completely overcome the copper fine line resistivity effects at the physical line width of <40nm at the 22nm node, resulting in dramatic degradation of RC performance. In fact, the 45nm node gains in keff might only just offset losses due to the line resistance increase.
The question of how interconnect scaling will proceed remains. Potential rudiments in the so-called 'future connectivity' area point to the use of carbon nanotubes, optical or RF transmission systems. Yet these technologies, if at all viable, will not provide a definite solution in the mid-term future.
Near-term, cost-effective interconnects are more likely to focus on 3D technology and heterogeneous integration. 3D technology involves stacking ICs physically and connecting them through vias on the chips. Heterogeneous integration enhances established interconnect schemes with advanced ones at specific points within the semiconductor.
The underlying principle is to keep trans-mission lines short. While likely only to extend existing interconnect schemes by one or two generations, heterogeneous integration and other, future forms of connectivity might give rise to a true long-term solution.