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Bridging the Design Gap


1 September 2004


The cumulative trials of miniaturisation and differentiation are forcing integrated device manufacturers to reassess the production chain. René Penning de Vries of Philips Semiconductors makes the case for a resource-sharing approach that can be applied all the way along.


Semiconductor suppliers serving the consumer electronics industry are facing a challenging period. Yet this challenge does not lie exclusively in the race for ever-smaller process geometries. The way the industry will design the consumer-product chips that are produced at these next-generation technology nodes is also under debate.

GOING SUB-100NM

"Thanks to cumulative learning in the industry, the shift from 200mm to 300mm wafers has been less painful than previous transitions."

In process technology development, the move from 0.18µm to 0.13µm proved problematic. The introduction of low-k di-electrics, damascene and copper interconnect at 0.13µm took their toll on R&D costs. However, with no significant new materials or processes involved, the shift from 0.13µm to 90nm has been less taxing.

In terms of capital investment, the shift from 200mm to 300mm wafers has involved high levels of expenditure (mainly on new equipment and wafer fabs). But cooperations and joint ventures, such as the Crolles2 Alliance between Philips, STMicroelectronics and Freescale Semiconductor, have proven highly efficient strategies for minimising cost.

Thanks to cumulative learning in the industry, the shift from 200mm to 300mm wafers has been less painful than previous transitions. For 300mm-wafer processing, there is a greater degree of standardisation in terms of equipment, software protocols and process flows than before. This is not surprising considering the small number of 300mm-wafer fabs that have been set up, the dominance of a few equipment suppliers and the existence of well-defined ITRS roadmap performance requirements for sub-100nm technology nodes.

The result is that the process of getting advanced chip production lines operating has been speeded up, with the industry undertaking less process optimisation than was previously the case. For example, the 300mm-wafer fab established in Crolles, France, by the Crolles2 Alliance began pilot production of 120nm CMOS in 2003, followed by 90nm CMOS in early 2004. Right-first-time silicon was achieved from it almost immediately. By the end of 2004, the fab was ramping into volume 90nm production – faster than for previous CMOS processes.

With few players able to afford sub-100nm CMOS manufacturing on 300mm wafers, and with standardisation resulting in similar yields and production costs, the scope for winning business by claiming that the yield can be released, thereby reducing chip cost, will be limited. So, cost will not be a major factor in differentiating one IDM from another at the 90nm and 65nm CMOS nodes; it will probably not be so at 45nm or 32nm either. What will differentiate one IDM from another will be its ability to design the chips that customers need in a predictive, short time-to-market manner.

PROVIDING SYSTEM SOLUTIONS

Changes in the value chain make it essential for semiconductor suppliers to provide an ever-expanding amount of embedded software with their silicon. Although this represents real cost, its corresponding value is not always recognised. In practice, the point is rapidly being reached where designing the entire hardware/software system and leaving customers to add some high-level programming and box design is the norm. Add to this the fact that the convergence of computing, communications and multimedia is making these systems more complex at both hardware and software level, and it is not difficult to appreciate why IDMs face escalating system design costs and potential IP gaps.

"Cost will not be a major factor in differentiating one IDM from another at the 90nm and 65nm CMOS nodes."

One trend in the technologies chain has become highly visible: at the upper end of the chain, system and software requirements are more complex, with even a simple stand-alone application such as a TV set now requiring tens of megabytes of embedded code. In the future, 'media centres' will handle multiple audio/video formats while communicating via multiple wired/wireless interfaces. Operating system and application code development for these centres will be a huge and expensive task.

One way to mitigate the costs implied in such development is to generate well-defined application programming interfaces between the operating system and the middleware layers. This will enable independent software vendors to participate in software creation. Another solution is to develop, promote and adopt open standards on which software layers can be based. This helps to move software development costs away from IDMs, and encourages the emergence of technology ecosystems that have the critical mass to move things forward quickly. Open software and middleware standards are some of today's best examples of IP sharing.

In the same way that the complexity and costs of advanced CMOS process development and production has brought companies together, the increasing complexity of system IP and embedded software will drive cooperation at the level of hardware and software IP design and development.

IP CREATION AND INTEGRATION

From now on, a much higher level of resource sharing at all stages in between software design and chip production will occur. It will be apparent in the area of IP creation and integration, with all the resultant IP coming together either on a single piece of silicon or as part of a highly integrated system-in-package solution to create the convergence products of the future. The winners will be those companies that have access to all the required IP areas.

"Open software and middleware standards are some of today's best examples of IP sharing."

The first phase of the Crolles2 Alliance was related to CMOS process development and pilot manufacturing, but it has been extended upwards into the system design process to include common cell-libraries, and downwards in the manufacturing process to include common assembly and test methods. Given the trends in the industry, further expansion to the scope of pre-competitive cooperation is likely.

As to whether or not this model will work, Philips' own experiences over the past years provide some clues. Philips has a long history in IP-reuse, with its CoReUse (hardware) and MoReUse (software) internal re-use programs having been in place for over five years. At the end of the 1990s, the programs were refined into the design methodology behind Philips' innovative Nexperia family of programmable system-on-a-chip, companion integrated circuits, software and reference designs for consumer-product multimedia applications.

Before the development of this re-use orientated design methodology, IP creation was primarily aligned with the product roadmaps of the company's different business lines. These business lines represented a group of separate IDMs that shared a common set of libraries and semiconductor process technologies.

With this vertical focus on IP creation, it was not always easy to persuade individuals that they should put in the extra effort needed to create IP that was re-usable outside their immediate product roadmaps. Nor was it easy to persuade them to timeline their IP creation in ways that extended beyond their product roadmaps. Yet this was exactly what Philips' CoReUse and MoReUse programs succeeded in doing – not by imposing dictates from above, but by providing people with effective re-use standards and giving them an incentive to use them. Out of this came the environment in which the Nexperia concept flourished and the single most-important driver of the high 'right-first-time' rate for Philips' 90nm SOC silicon from the Crolles2 wafer fab.