The pressure of Moore's Law and the need to keep costs low demand a new approach to equipment development. Collaboration could be key. Barbara Levine, Alan Furlano and Jack Uppal of Intel Corporation discuss the indicators for a new collaborative model.
Over the last 30 years, innovation from semiconductor companies and equipment suppliers has propelled the silicon industry into the sub-100nm nanotechnology era. The engines have been microprocessors and memory, the drumbeat Moore's Law, and the fuel is research and development.
Moore's Law has already been extended to 65nm. Experimental devices with less than 10nm gate lengths have been successfully demonstrated. New nano materials, processes and structures could extend Moore's Law well into the second decade of this century. However, there are formidable challenges: cost (per bit or transistor) must continue to decline; technological complexity is increasing; and integration must keep pace.
These challenges dictate ever-closer collaboration between users and suppliers of semiconductor materials and equipment. And taking into account that obstacles to the introduction of new materials (such as low-k inter-metal and hi-k gate dielectrics) lie not in forming the appropriate films, but rather with integrating these materials into a complete process, some conclusions can be made about the shape of future silicon R&D.
The declining cost of silicon technology products is obvious to any consumer who has purchased computer products over the past 20 years. Not only are computer prices down to sub-$500 prices, but also the cost of supporting products such as DRAMs and hard disks has followed a similar trend.
The ASP of a product (such as a microprocessor) has been flat to down, while the number of devices inside that product (transistors or memory bits) has grown exponentially. This is possible only with these requirements: scaling of silicon technology to increase circuit density; keeping wafer, packaging and test costs flat to down. This is where the main challenge becomes most evident.
Whereas scaling requires the introduction of new process modules and added metal and lithography layers, the market has required wafer costs to remain flat to down. So far, this has been achieved successfully.
The major components of wafer cost are equipment depreciation, materials (chemicals, gases, silicon wafers), facility depreciation, direct and indirect headcount, and sufficient margins to absorb R&D costs. Under unrelenting competitive cost pressures, the industry has managed to make important reductions in headcount (through automation) and facility costs (through the use of mini-environments). Materials costs have not declined as much, although improvements to process equipment have led to lower chemical consumption (on a per die basis). However, equipment depreciation and R&D costs remain major challenges.
Equipment depreciation concerns have been partially alleviated by the wafer size transition to 300mm, which will hopefully lead to other affordability solutions for new process equipment and continuous improvement in equipment capital output. However, the R&D costs at equipment suppliers and the need for timely, affordable manufacturing equipment for new technologies will drive a shift in the equipment development model.
R&D AND REVENUE
In the past, the industry model was for semiconductor companies to buy equipment, along with at least a basic process recipe, and then complete integration work for implementation. This placed a large burden on equipment companies to not only develop the equipment, but also to do some recipe and process development.
In the late 1990s, several equipment companies started to form 'integration' centres to do this development work. This increased development activity is reflected in the R&D spending at equipment companies over the last few years.
For the major equipment suppliers, R&D spending reached a maximum of 20%–25% of revenue during this period (the average being 15%). The sustainability of this spending is questionable, especially during cyclical industry downturns when fixed R&D budgets can rocket to more than 30% of revenue. To maintain break-even points, equipment companies may be forced to cut funding to vital programmes.
There has been a realisation this decade that equipment and recipes alone are increasingly insufficient for integration. This is reflected in the ITRS roadmap for the keff-value of inter-metal dielectrics of 1994, 1999 and 2003. In 1994, the need to go to lower k inter-metal dielectrics was apparent, and few obstacles were anticipated. Several equipment companies developed CVD equipment and/or spin-on materials to meet those needs. But when semiconductor companies tried to integrate these films, which are inherently soft, into the rest of the process, they found that there was no reliable integration solution: the ITRS roadmap for keff-values was much less aggressive in 1999 and less so in 2003. Nevertheless, equipment companies had sunk R&D spending into this area, which is not likely to result in any revenue for some time.
The case of low-k dielectrics was an eye-opening experience for equipment companies. R&D spending based only on the speculative needs of semiconductor companies was not sufficient to provide a reasonable likelihood of realising revenue. Instead, it was becoming more important for equipment development to occur parallel with process integration development. This meant that cooperation with device manufacturers was becoming necessary for sufficient integration work and successful validation of new equipment. The dawn of a new model for R&D spending at equipment and semiconductor companies had arrived.
Low-k was perhaps an early glaring example of the need for collaboration. Looking ahead, the challenges of strained silicon, hi-k gate dielectrics and metal gate materials, and new modules to support novel transistor approaches, such as tri-gate transistors, will all require joint work on equipment and materials to be successful.
Setting up a collaboration model is not easy. Although several companies already use the model, precise details of how to do so are still evolving. The major difficulties revolve around how jointly developed IP is treated, and how both companies can derive some kind of advantage over their respective supply chain competition. Still, it is possible to formulate some key factors for a successful collaboration.
Does a collaboration model preclude smaller equipment companies and start-ups? Not necessarily. The requirement that suppliers deliver manufacturable equipment (with service and spares across a global infrastructure) will make life difficult for a fledgling company, but collaboration can help identify solutions to infrastructure problems parallel with equipment development. Also, collaboration with suppliers is not a model just for semiconductor companies. If it is extended to equipment companies, then collaboration with smaller sub-suppliers will become feasible.
KEEPING PACE WITH CHANGE
A collaborative environment between equipment or material suppliers and silicon device manufacturers is evolving to become the mainstay of the silicon industry's alignment with Moore's Law. It is the best means for equipment companies to develop equipment that can be integrated into new technology nodes.
Solutions to how collaborations deal with IP ownership and competitiveness are being worked on, and these will evolve into win-win models benefiting suppliers and manufacturers. Through collaborations, silicon technology should continue at its present pace for several generations, despite the enormous changes that the technology will inevitably undergo.