Soaring manufacturing costs have seen the industry's major players team up to undertake design and production jointly. Jim McGregor, In-Stat, outlines the successful coming together of three industry leaders.
The cost of semiconductor manufacturing continues to climb and drive changes in the market. Not only have state-of-the-art 90nm and 65nm fabs now reached an average cost of nearly $5bn, but the cost of developing the process technology also continues to rise with each generation. Likewise, the expense of manufacturing continues to increase. The cost of developing mask sets, which are unique to every product and usually every fab, exceeds $1m a set and is expected to continue to increase exponentially with each process node.
These rising costs and other market dynamics have combined in the past to drive the separation between fabless semiconductor companies and foundry models that are predominant today.
The same trends are shrinking the number of semiconductor companies with fabs and foundries to below 40. Many semiconductor manufacturers and foundries have turned to joint process technology development, which addresses one side of the cost equation. There are at least three major alliances aimed at developing advanced CMOS process technology: IBM's SOI Alliance, Crolles2 alliance and the Advanced SoC Platform Corporation (ASPLA).
Chartered Semiconductor Manufacturing, IBM and Samsung have now developed a new model that addresses both the cost of fab capacity and process development, while providing a cohesive design ecosystem through their Common Platform™ technology.
They have extended their joint bulk CMOS development alliance to include joint manufacturing capability. The Common Platform technology partners have generated a number of new benefits for clients, including:
- Full product development, manufacturing and product lifecycle support from three leaders in semiconductor design, process technology and manufacturing
- Multi-sourcing a single design through GDSII compatibility to globally diverse synchronised fabs for risk mitigation and/or upside support
- Choice of design enablement resources (libraries, IP, reference flows, EDA tools and packaging), including a robust set of design-for-manufacturing (DFM) tools jointly supported by multiple tool vendors, design centres and foundry partners
- Engineering services and support from three companies with expertise in every aspect of semiconductor design and manufacturing
The Common Platform technology alliance has established a new model for semiconductor design and manufacturing through a new level of collaboration among industry leaders.
MANUFACTURING CAPACITY AND EFFICIENCY
The Common Platform technology collaboration was formed on a key transition point for the industry: 300mm wafers. This is a boundary that precludes many smaller players from entering or continuing in the manufacturing realm, but provides a significant increase in capacity for those that can. Just the use of 300mm wafers provides an average increase of two-and-a-half times in volume of chips per wafer.
Only 21 companies have announced plans to build 300mm fabs, and of the 18 in operation, the combined manufacturing capacity of the Common Platform technology partners with the current fabs fully ramped represents 22% of total capacity and 60% of foundry-only capacity. In addition, both Chartered and Samsung have indicated that they are considering further expansions of their existing 300mm fabs to 70,000 wafers a month and/or the construction of additional fabs in the future.
The fact that the three entities are all focused on continuously improving yields has led to improved fab efficiency at all three foundry partners. IBM and Chartered have already benefited from the relationship through the development of an advanced set of technology elements at the 90nm node, and all three companies are reaping the benefits from this learning at the 65nm and 45nm nodes.
Although Samsung has dedicated the S1 fab to the Common Platform technology, it continues to invest in additional 300mm fab capacity for its other semiconductor product lines, which could potentially be used for foundry purposes if necessary. For the client, the current and potential capacity at three companies translates into quicker time to market, higher delivery reliability and greater elasticity to handle demand swings.
UNMATCHED PROCESS EXPERTISE
Although the Common Platform technology is aimed at semiconductor manufacturing, it is an extension of the IBM CMOS development alliance. Through its industry-leading expertise in process technology and other relationships, IBM brings a wealth of knowledge and expertise to the development process.
Overall, there are seven semiconductor foundries and IDM companies working on developing new process technologies together in Fishkill, New York, which is unmatched by any other development alliance or individual company.
On 29 August 2006, the CMOS development alliance, consisting of Chartered, IBM, Infineon and Samsung, announced the first circuits manufactured on a 45nm process and the availability of early design kits. The process will be one of the first in the industry to use immersion lithography.
Although the use of immersion lithography adds additional challenges to manufacturing, the 45nm CMOS process will be installed and qualified at Chartered, IBM and Samsung by the end of 2007. Other semiconductor vendors, such as Intel, have indicated that they will not be using immersion lithography until a later process node, but that it will likely be required. The 45nm process development effort included 200 engineers from the four development partners.
INCREASED ENGINEERING RESOURCES
Just as the global diversity of the manufacturing sites mitigates risk, it also provides more manufacturing and engineering support. With the fabs located in Singapore, South Korea and the East Coast of the US, multiple engineering teams at multiple fabs can work to resolve issues and improve manufacturing efficiency around the clock, rather than a single fab and engineering team in the traditional foundry model.
With knowledge in different products, the Common Platform technology partners also offer a wide range of expertise and experience. This knowledge and support can be critical during the ramp of a new product. With three distinct companies joining together to coordinate yield ramps, various resources have been cross-geographically leveraged. Such resources include wafers and indigenous processes for yield learning and engineering talent and have led to cost reductions and industry-leading ramp times.
In addition, when a change is introduced or one location experiences a problem, engineers from all three locations can work to resolve the issue and prevent the complete shutdown of individual or multiple lines. The result is a constant flow of information that has the potential to provide both current and future benefits to the fabless semiconductor customers.
Another key advantage to the Common Platform technology is the common resources that are available, including intellectual property (IP), libraries and tools. As IDMs, Samsung and IBM naturally have a considerable amount of IP available. Likewise, as foundries, Chartered and IBM have a considerable amount of licensable IP available.
Since the processes and fabs are synchronised, once the IP is qualified at one fab, it is qualified for all of the fabs. In a similar manner, the Common Platform technology has licensed third-party libraries from both ARM (formerly Artisan) and Virage Logic for the 90nm process node and ARM for the 65nm and 45nm process node.
The importance of tight links between the EDA tool vendors and the technologies that are being used for chip design is becoming evident at 65nm. It is no longer acceptable to add margin to simple corner-based models and force designers to close timing, noise, power and yield targets by working around impossible guard bands.
The Common Platform technology partners are including process and manufacturing data, not just to ensure good DFM practice, but also to work with the leaders in the EDA industry to ensure that chip designers are able to understand the impact that subtle shifts in the process will have on their designs' functionality and specs.
This is achieved by all the partners working with Cadence, Magma, Synopsys and others, so that these effects can be modelled in an open fashion. Having reference flows from these companies that take into account the effects seen by the process experts is a requirement for anyone contemplating design at 65nm and beyond.
The final shared resource is tools. A critical attribute of the Common Platform technology is a common suite of third-party DFM tools. The purpose of the DFM tools is to bring the critical aspects and considerations of the desired manufacturing process earlier into the planning and design process of the product.
Using DFM allows designers to make decisions in the design that may affect various attributes of the product in manufacturing, such as power, thermal, timing and signal integrity, as well as minimising the die size and time to market. Achieving desired cost, performance and yields often requires trade-offs in many of these attributes.
At the 90nm and 65nm process nodes, the Common Platform technology offers a design enablement kit and DFM rule and utility kit, both designed jointly by the group. The kits provide design lines for developing products for the manufacturing process.
The three fabrication partners have inherent differences in goals from the alliance and distinct cultures. Yet they have embraced the complexity of synchronising a single process across multiple fabs with due diligence. They are working to resolve geographical and equipment-related differences. Thus far, however, Chartered, IBM and Samsung have integrated their processes, teams and strategies very efficiently.
Companies with multiple fabs typically follow a copy-exact mantra to eliminate most factors that could introduce variance in the manufacturing process. As the largest semiconductor manufacturer in the world, Intel has almost perfected this effort, which often leaves environmental conditions as the only potential issue.
Although the Common Platform technology partners work together in evaluating equipment, fab equipment is often different, due to variations at the time the fabs are equipped, and differences in contractual agreements and service and support from the equipment vendors. In addition, each company uses some elements of IBM's SiView fab automation tools, but each vendor customises it to their own requirements.
The partners are working, however, to reduce the variance as much as possible. Approximately 70% of the equipment used by IBM's 323 Fab, Samsung's S1 Fab and Chartered's Fab 7 is the same, including critical lithography systems. The existing differences do not pose risks with respect to process-matching. The differences between tools from various equipment vendors are, however, being reduced as more of the operational specifications are being driven by process development alliances, such as the two being led by IBM for bulk CMOS and SOI.
DIFFERENT MASK SETS
Although the processes at each fab are GDSII-compatible, each fab requires a different mask set for each product that is not compatible between fabs. This adds the cost of additional mask sets, which average over $1m a chip for the 90nm process node.
The use of different mask sets, however, mitigates schedule risk with the development of the masks and allows for easier debugging of masks if one set passes and another fails, as IBM and Chartered found with the first- and second-generation Xbox 360 processors. The additional cost of different mask sets, however, may be minimised by the internal mask development resources at IBM and Samsung.
The cost may also be quickly offset by the rapid ramp in product volume at multiple fabs. Going forward, the Common Platform technology partners are working to use similar mask designs to collaborate on yield ramps and process integration.
The fact that each of the partners has a different business model adds a layer of complexity as well as versatility. IBM, which has been a leader in semiconductor process technology, has recently moved to a model that combines foundry manufacturing with ASIC and server development along with other engineering services.
Chartered is a pure-play foundry, and it is continually expanding its expertise in process development, even solidifying a relationship with Amkor, a leading packaging company, after selling its Fab 1 building to Amkor for on-site package development and packaging services.
Samsung, on the other hand, is one of the largest electronics conglomerates, with significant success in Plasma TVs, LCDs and mobile phones over the past five years, in addition to its leadership in semiconductor memory. Samsung has recently announced that it will be offering engineering and logic foundry services.
Although the different goals of the companies would seem to be at odds, they are actually very symbiotic. Just as IBM looks to target high-volume applications, the company can use Chartered and Samsung for foundry resources in addition to its own capacity.
In a similar manner, as Chartered does not offer the product development engineering services, it can look to IBM and Samsung for that expertise. This also extends to the future strategies of each partner. Both IBM and Chartered admit that they could not have won the Microsoft Xbox 360 processor contract without their common manufacturing and fab ramp initiatives. Chartered could not have supplied the product development resources and IBM could not have supported the manufacturing requirements. Now other existing customers and partners of the Common Platform technology group are reaping the benefits as well.
Although the current agreement for the Common Platform technology extends through 2007, discussions are already underway for further extensions of this relationship.
The high investment in process development; resources allocated to evaluate equipment, fab ramp and synchronisation fabs efforts; and the benefits each partner stands to reap from the relationship provide strong justification for a long-term relationship. If anything, it increases the possibility of other partners in the future, a scenario that none of the existing partners will rule out.
The cultural differences would appear to be by far the most challenging obstacle to overcome. Not only is each company located in a different region with a different culture and language, but each company is also a major competitor in their respective segments of the semiconductor market.
Many of these barriers have been overcome with time and close working relationships. During the ramp of the 90nm process at Chartered and the ramp of the Xbox 360 processor, Chartered and IBM employees maintained continuous contact through on-site meetings, and rigorous use of test vehicles for synchronising the performance of the fabs. Although Samsung entered the programme at a later stage, similar relationships have been developed, as all three companies work jointly on a new product effort for QUALCOMM, a leader in communications technology.
These close working relationships have also overcome delays customers would expect in dealing with more than one company by having project leads from each partner assisting in coordinating communications. Automated data sharing techniques are being set up between all three partners for continuous communication and troubleshooting.
The presence of development engineering teams from all three companies in Fishkill provides a great melting pot for assimilating cultural differences and focusing on the broader common goal of winning in the marketplace.
A SUCCESSFUL ALLIANCE
With the formation of several major technology alliances aimed at developing future process technology, there is a clear trend toward the co-mingling of development resources that are becoming part of the new semiconductor business model.
Chartered, IBM and Samsung have accomplished what would have seemed impossible a decade ago because of the difficulty of combining the resources of three companies with different products, market strategies and cultures, and extending the development model to include joint manufacturing capabilities.
However, necessity driven by increasing development and manufacturing costs has proven to be a catalyst for industry change once again.
This new model is gaining tremendous momentum with at least 14 design tool / EDA / IP partners joining to provide a comprehensive design ecosystem plus the industry-leading packaging vendor, Amkor. In the latest report on fab synchronisation, all three factories are centred on all 65nm low-power device parameters within less than 5% deviation.
The Microsoft Xbox 360 processor demonstrates IBM's and Chartered's fab synchronisation and manufacturing capabilities. Subsequently QUALCOMM is leveraging the platform's benefits for 90nm production and beyond. The Common Platform technology also has a strong roadmap for future technology development and capacity expansion.