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Photonic Integration: The Next Small Thing


1 February 2007


The quest for greater processing speed is now focusing on achieving more efficient data flow within systems. TC Chen reports on an IBM project that uses optical devices to enhance computer performance.


Today's more powerful microprocessors would be capable of much higher work levels if a means could be found to increase the flow of information in a computer. As chips are able to process more data, optical communications could be the way to eliminate bottlenecks. As a result, the focus in high-performance computing is shifting from improving computation to enhancing communication within the system.

Long delays can be achieved by passing light through optical fibres. However, current 'delay line' devices are too large for use on a microchip, where space is precious and expensive. For practical on-chip integration, the area of a delay line should be well below 1mm² and its construction should be compatible with current chip manufacturing techniques.

IBM scientists have managed to meet this size restriction and achieve the necessary level of control of the light signal by passing it through a new form of silicon-based optical delay line built of up to 100 cascaded micro-ring resonators. These are built using current silicon complementary metal-oxide- semiconductor (CMOS) fabrication tools.

When the optical waveguide is curved to form a ring, light is forced to circle multiple times, delaying its travel. The optical buffer device based on this simple concept can briefly store ten bits of optical information in an area of 0.03mm² – that corresponds to 10% of the storage density of a floppy disk. This advance could lead to the integration of hundreds of these devices on a single computer chip – an important step towards on-chip optical communications.

This exploratory project pushes the limits of current photonic technology. Its ultimate goal is to develop a technology for the on-chip integration of ultra-compact nanophotonic circuits for manipulating light signals, similar to the way electrical signals are manipulated in computer chips.

Integration of optical devices at the chip scale is seen as a key to significantly reducing the cost of optical components. Dense photonic integration might enable a whole new area of optical interconnects to be economically viable.

Eventually, the development of nanophotonic technology compatible with CMOS fabrication could result in the cheap mass production of densely integrated optoelectronic superchips comprising both photonic and electronic circuitry.

INTEGRATED PHOTONIC AND ELECTRONIC CIRCUITS

This hypothetical chip performs all-optical routing of mutliple (N) optical channels, each supporting a 10Gbps data stream. N channels are first demultiplexed in a WDM photonic circuit, then rearranged and switched in an optical cross-connect OXC module, and finally multiplexed back into another fibre with new headers in a WDM multiplexer.

"It is difficult to achieve practical chip-level optics because the components take up precious space on the chip."

Data packets are buffered in an optical delay line if necessary. Channels are monitored with integrated Ge photodetector PD. CMOS logical circuits (VLSI) monitor the performance. Electrical pads connect the optoelectronic chip to other chips on a board via electrical signals.

Silicon-on-insulator (SOI) is an attractive platform for photonic integration, owing to its high refractive index, which offers strong light confinement and therefore ultra-compact devices. On the other hand, by adopting a substrate material that is CMOS-compatible, decades of materials and process knowledge can be leveraged. It is feasible that both passive and active optical elements could be combined with electronics on a single chip.

HOW SMALL?

IBM is trying to establish just how small photonic devices can be. This is a very interesting question from a research point of view, but is also of great practical importance. If IBM's goal is to integrate a large number of optical devices on a microprocessor chip, then miniaturisation is a key here.

At the same time, the company is exploring the integration of optical and electrical circuits on the same silicon chip, using the same processing steps that are used for the manufacture of microprocessors. In general, the broad goal of IBM research is to build a photonic device toolbox containing a variety of devices, such as modulators, filters, WDM devices, detectors and so forth.

Finally, by scaling photonic devices and integrating them with CMOS electronics, IBM wants to build on-chip optical networks. The demonstrated optical buffering device is just one of the photonic devices needed for such a complete toolbox.

Optical buffering can be used to help direct the busy information traffic on a chip and avoid traffic congestion. Signal congestion at the switching nodes, which occurs when two data streams arrive at the switch at the same time, is a problem in any network. Without an optical buffer, buffering has to be realised in the electronic domain. Optical signals have to be converted into electrical signals and stored in electrical memories, after which they are converted back to optical domain-using lasers.

"Bottlenecks in data flows are currently slowing down even the fastest processors."

However, such a solution is almost impossible for on-chip applications because thousands of detectors and lasers would be required. For on-chip networks, buffering directly in the optical domain has obvious advantages of simplicity, power and cost efficiency.

The buffering of optical signals itself is an easy task. If we let the optical signal pass through a long optical fibre, we can achieve a long time delay. We can even coil a long fibre into a relatively small device. However, such a device would be much larger than the whole area of a microprocessor chip. To be viable for on-chip applications, optical buffers should be extremely small.

ON-CHIP FOOTPRINT REDUCTION

The basic building block in IBM's demonstration, silicon submicron photonic wire waveguide, has a cross-section of below 0.1μm². Optical delay can be realised using this waveguide, but we would need about 7cm of the waveguide.

In IBM's tests, it used optical micro-resonators based on these waveguides to decrease the device area, since footprint is very expensive. By bending a photonic waveguide and forming a micro-ring, light can propagate many times in the ring when the light wavelength is tuned to the ring resonance, and hence the delay can be significantly enhanced.

Apart from showing record fractional delays of ten bits on a silicon chip, one of the major advantages of IBM's demonstration is its extremely small device area. The device demonstrated in this paper has a footprint as small as 0.03mm². This is a direct result of utilising the nanophotonic waveguides.

IBM used a photonic wire waveguide with a cross-section smaller than 0.1μm² and a very high index contrast between silicon and air or oxide cladding. As a result, it was possible to bend the waveguide at a radius in the order of just a few microns, while the loss per 90º bend can be as small as 0.004dB. Rings with such a small radius can be made in this way, while keeping losses very small.

"IBM has produced an on-chip optic on a conventional production line."

THE PATH TO COMMERCIAL APPLICATION

Optical storage of ten bits is enough to encode one ASCII character. However, to make an optical buffer useful for on-chip optical networks, whole packets of optical signals should be buffered. We would need to delay hundreds of bits. Despite the huge potential of on-chip silicon photonics, we still have a long way to go. The current device is just a first step along this road.

A reasonable estimation would be that somewhere between ten and 15 years from now we can expect optics to appear on a microprocessor chip. However, some specialised silicon-based photonic devices integrated with CMOS electronics can go to market earlier in the shorter term, for example as components for telecommunications. Several companies are currently working in this particular area and they are making very good progress.

The next obvious step is to increase buffering capacity to store hundreds of bits. Currently, capacity is limited by the relatively large 20dB losses that are accumulated in a delay line, but IBM plans to decrease the loss numbers further. Another goal the company is seeking to achieve is the electrical tunability of a delay time by applying electrical current to the nanophotonic waveguide. This would allow the active tuning and manipulation of optical signals with electrical input.