ChipPAC

ChipPAC assembly and test foundry, Shanghai, China.

ChipPAC is more than doubling its capacity at Shanghai.

The ChipPAC facility will be over 30,000m2.

Leaded packages include the iQuad(1) with up to 208 leads.

ChipPAC has announced its intention to build a facility that will more than double the company’s capacity at its site in the Qingpu District of Shanghai. Planned to begin Q3 2003, the facility will be over 30,000m² and will be brought on stream when
existing capacity is full (currently running at around 85%). When the new fab does come on stream, it should produce, test and distribute over ten million units per day (rising long-term to 14 million per day).

ChipPAC has already invested more than $150 million in manufacturing capabilities in China and plans to expand turnkey assembly and test business there still further. With so many IC manufacturers setting up around the city, the company aims to become a logistics and distribution hub for semiconductor companies wanting to do business in China.

Recently named an Intel Preferred Quality Supplier, ChipPAC has been adding customers in fast growth wireless, broadband, mobile and automotive markets and consumer equipment like DVD players and set-top boxes.

MULTI-DIE PACKAGES

ChipPAC began production in China in 2001 with chip scale packages and has since developed a number of others including multi die types. The existing foundry is located in Shanghai’s Xi Jiao Economic & Technological Development Zone. The 4,430m² QS-9000 certified facility has floor space available for customers’ captive lines.

The company offers a range of packaging options for both SMD leaded and laminate designs. Leaded packages include:

• Dual in line packages (PDIP, PLCC), small outline packages (SOIC, SSOP, TSOP I and II and TSSOP)
• Quad flat packs (TQFP, MQFP, LQFP) and I-Quad I and IV

Laminate packages concentrate on:

• Ball grid arrays (the most advanced mass produced package, with solder ball connections at bottom: PBGA and EPBGA, µBGA, FBGA-T, TBGA)
• Chip scale packages (where the component size after packaging is roughly the die size: Flip Chip CSP, EconoCSP”, LFCSP” and M²CSP”)

Packaging services for wireless and wire line communications semiconductors include stacked die technologies. The company also provides custom design services and thermal, electrical and mechanical characterization.

New 90nm silicon processes will require even smaller bond pitch and higher I/O count. In response, ChipPAC has recently announced three-row staggered wire bonding at 20 micron effective pitch for greater than 1,200 I/O pad limited ICs. Three rows of
60 micron pitch wire bond pads connect the die to five rows of bond-fingers/rings on the package substrate. The package brings wire bonding to a wider range of applications like graphics and ASIC chips. These can now stay with low cost wire bond BGAs rather than the flip chip packages that can have triple the costs.

ALLIANCES INCLUDE ANALOG, POWER AND SMART CARD FOUNDRY

ChipPAC has allied with a number of companies, notably ASMC, SMIC and Grace Semiconductor Manufacturing Corp (GSMC) to provide end-to-end IC manufacture.

The alliance with analog/power/smart-card wafer foundry ASMC for example allows the two companies to offer end to end solutions from wafer fab to wafer sort, packaging, final test and distribution.

The companies note a growing trend to outsource semiconductor manufacturing in analog and power (an attractive market for manufacturers since they are needed in all types of electronic products).